1. Field of the Invention
The present invention relates to a receiving apparatus suitable for directly receiving a digital direct satellite broadcast, a receiving method therewith, and a digital PLL circuit therewith.
2. Description of the Related Art
A digital direct satellite broadcast has been performed. In the digital direct satellite broadcast, a video signal is compressed with highly efficient encoding technology corresponding to MPEG (Moving Picture Expert Group) system and a digital video signal and a digital audio signal are broadcast by a satellite has been performed. FIG. 15 shows an example of a receiving system of such a digital direct satellite broadcast.
In FIG. 15, reference numeral 101 is a satellite that performs a digital satellite broadcast. Reference numeral 102 is a parabola antenna that receives a broadcast signal from the satellite 101. Reference numeral 103 is an IRD (Integrated Receiver/Decoder) that demodulates a video signal from the received broadcast signal. Reference numeral 104 is a monitor that displays a received picture.
A stream of a digital video signal corresponding to the MPEG (Moving Picture Experts Group) and a digital audio signal are sent with a 12 GHz band carrier through the satellite 101. A signal sent from the satellite 101 is received by the parabola antenna 102. The parabola antenna 102 is provided with an LNB (Low Noise Block Down-converter) 105. The signal received by the parabola antenna 102 is down-converted into a signal with a predetermined frequency by the LNB 105.
An output signal of the LNB 105 is supplied to the IRD 103. The IRD 103 comprises a tuner circuit that selects a predetermined channel, a demodulating circuit that demodulates a bit stream, a demultiplexer that separates the bit stream into video data and audio data, an MPEG video decoder that decodes an MPEG video signal, an analog video encoding circuit that generates for example an NTSC composite video signal with the decoded video signal, and an MPEG audio decoder that decodes the MPEG audio signal. The signal sent through the satellite 101 is demodulated by the IRD 103. An output signal of the IRD 103 is supplied to the monitor 104.
As described above, in the digital direct satellite broadcast, the MPEG system is used. With the highly efficient encoding technology, a video signal is compressed. The compressed video signal is sent along with a digital audio signal. In the MPEG system, the digital video signal and the digital audio signal are sent as a stream of packets. A time stamp is placed to each decode/reproduction unit of the video signal and audio signal. The decode/reproduction unit is referred to as access unit. The time stamp is composed of a PTS (Presentation Time Stamp) and a DTS (Decoding Time Stamp). The PTS is time management information of reproduced output data. The DTS is time management information of decoded data. The time stamp and an STC (System Time Clock) that is reference time are compared. When the time stamp accords with the reference time, the relevant access unit is reproduced.
To designate a time reference, an SCR (System Clock Reference) and a PCR (Program Clock Reference) are sent. To calibrate the value of the STC as the time reference, the values of the SCR and PCR are used. The system clock is oscillated with a PLL that is in association with the STC.
In other words, the PLL comprises a VCO that oscillates a system clock at a frequency of 27 MHz, an STC counter that counts with an output signal of the VCO, a phase comparing circuit that compares the value of the SCR or PCR with the value of the STC counter, and a loop filter to which output data of the phase comparing circuit is supplied. The STC counter is set with the received SCR and PCR. With output data of the phase comparing circuit through the loop filter, the VCO is controlled.
In the PLL that compares the value of SCR or PCR with the value of the STC, in the control start stage, the loop should be quickly pulled and locked so that the value of the STC accords with the value of the SCR or PCR. In the signal receive stage, the signal should be stably controlled. If the phase difference between the value of the STC and the value of the SCR or PCR exceeds a predetermined range and thereby the loop is unlocked due to any region, the phase difference between the value of the STC and the value of the SCR or PCR should be quickly pulled in the predetermined range.
However, it is difficult to satisfy all these conditions. In other words, in the case that the gain of the PLL is high, since the loop can be quickly pulled, it is advantageous in the control start stage. However, when the loop gain of the PLL is high, in the normal receive state, the PLL does not stably operate.